c++ - Preventing or blocking cpu data cache loading

I'm tasked with evaluating various flavors of ARM processors (benchmarking), specifically System On a Chip (SOC). Some SOC's have a lot of data cache, others have little. Because of this, I'd like my program to block the data cache.

I have written a Walking 1 test which accesses memory outside the core, but on the SOC. I'm going to run this on our present processor, that has very little data cache, and run it on a Cortex M3 processor, which has a lot of data cache memory.

I'm focusing on durations to fetch memory outside the processor. If I set the size of memory for the Walking 1 to a size larger than the data cache, the to run the test "exponentiates" in time. For example, for a small size of memory, the test runs in minutes, for larger memory sizes, the test takes hours.

Question: Is there an idiom that can be used to prevent the processor from loading the entire array into the processor's data cache?
(Note: This is tagged as C and C++ because I have the option to choose between the languages. If C has no idiom, but C++ does, than I will try C++ first.)

• Platform: Various embedded or System On a Chip (development /
  evaluation boards), no OS.



• Processor: ARM Cortex series with different peripherals on the chip
  and different data cache sizes.


• Compilers: IAR Embedded Workbench, GNU C, GNU C++ (used in the
  background by various board suppliers).

Answer

Unless your compiler provides functions to access the memory region protection registers, you'll need to do some assembly to set memory region(s) to non-cacheable:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0290g/Chdhdahb.html

or as mentioned below globally disable level one data and instruction cache via bits 2 and 12 of the c1 control register, which is accessed via co-processor register 15 = CP 15:

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0338g/Babebdcb.html

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0338g/Babgdhif.html

This assumes that your ARM processors have CP 15 functionality. There may be other control registers that might be useful for your tests. I'm not sure how this would be done on ARM processors without CP 15 functionality.